Stress enhanced mos transistor and methods for its fabrication

ABSTRACT

A stress enhanced MOS transistor and methods for its fabrication are provided. In one embodiment the method comprises forming a gate electrode overlying and defining a channel region in a monocrystalline semiconductor substrate. A trench having a side surface facing the channel region is etched into the monocrystalline semiconductor substrate adjacent the channel region. The trench is filled with a second monocrystalline semiconductor material having a first concentration of a substitutional atom and with a third monocrystalline semiconductor material having a second concentration of the substitutional atom. The second monocrystalline semiconductor material is epitaxially grown to have a wall thickness along the side surface sufficient to exert a greater stress on the channel region than the stress that would be exerted by a monocrystalline semiconductor material having the second concentration if the trench was filled by the third monocrystalline material alone.

TECHNICAL FIELD

The present invention generally relates to MOS transistors and tomethods for their fabrication, and more particularly relates to stressenhanced MOS transistors and to methods for fabricating such transistorswith embedded material adjacent the transistor channel.

BACKGROUND

The majority of present day integrated circuits (ICs) are implemented byusing a plurality of interconnected field effect transistors (FETs),also called metal oxide semiconductor field effect transistors(MOSFETs), or simply MOS transistors. An MOS transistor includes a gateelectrode as a control electrode and spaced apart source and drainelectrodes between which a current can flow. A control voltage appliedto the gate electrode controls the flow of current through a channelbetween the source and drain electrodes.

The complexity of ICs and the number of devices incorporated in ICs arecontinually increasing. As the number of devices in an IC increases, thesize of individual devices decreases. Device size in an IC is usuallynoted by the minimum feature size, that is the minimum line width or theminimum spacing that is allowed by the circuit design rules. As thesemiconductor industry moves to a minimum feature size of 45 nanometers(nm) and even smaller, the performance of individual devices degrades asthe result of scaling. As new generations of integrated circuits and thetransistors that are used to implement those integrated circuits aredesigned, technologists must rely heavily on non-conventional elementsto boost device performance.

The performance of an MOS transistor, as measured by its currentcarrying capability, is proportional to the mobility of the majoritycarrier in the transistor channel. It is know that applying alongitudinal stress to the channel of an MOS transistor can increase themobility; a compressive longitudinal stress enhances the mobility ofmajority carrier holes and a tensile longitudinal stress enhances themobility of majority carrier electrons. It is known, for example, tocreate a longitudinal compressive stress to enhance the mobility ofholes in P-channel MOS (PMOS) transistors by embedding silicon germanium(eSiGe) adjacent the transistor channel. To fabricate such a device atrench or recess is etched into the silicon substrate in the source anddrain areas of the transistor and the trench is refilled by usingselective epitaxial growth of the SiGe. Simply increasing the germaniumcontent of the eSiGe to increase the stress, however, is not entirelysuccessful as increased germanium content results in increased SiGe lossfrom the surface of the embedded region, agglomeration of the metalsilicide formed on the embedded region to reduce contact resistance tothe source and drain areas, and increased stress relaxation of theembedded material as the transistor undergoes the more conventionalsteps encountered in fabricating the IC.

Accordingly, it is desirable to optimize methods for fabricating stressenhanced MOS transistors. In addition, it is desirable to provide anoptimized stress enhanced MOS transistor that avoids the problemsattendant with conventional transistor fabrication. Furthermore, otherdesirable features and characteristics of the present invention willbecome apparent from the subsequent detailed description and theappended claims, taken in conjunction with the accompanying drawings andthe foregoing technical field and background.

BRIEF SUMMARY

A stress enhanced MOS transistor having enhanced majority carriermobility is provided. The stress enhanced MOS transistor comprises asemiconductor substrate having a surface and a channel region at thesurface. A first region of SiGe having a first germanium concentrationis embedded in the semiconductor substrate. The first region has abottom portion and a side portion adjacent the channel region. A secondregion of SiGe having a second germanium concentration less than thefirst germanium concentration is embedded in the first region so thatthe side portion has a greater thickness than the bottom portion.

A method is provided for fabricating a stress enhanced MOS transistor.In accordance with one embodiment of the invention, the method comprisesforming a gate electrode overlying and defining a channel region in amonocrystalline semiconductor substrate. A trench having a side surfacefacing the channel region is etched into the monocrystallinesemiconductor substrate adjacent the channel region. The trench isfilled with a second monocrystalline semiconductor material having afirst concentration of a substitutional atom and with a thirdmonocrystalline semiconductor material having a second concentration ofthe substitutional atom. The second monocrystalline semiconductormaterial is epitaxially grown to have a wall thickness along the sidesurface sufficient to exert a greater stress on the channel region thanthe stress that would be exerted by a monocrystalline semiconductormaterial having the second concentration if the trench was filled by thethird monocrystalline material alone.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will hereinafter be described in conjunction withthe following drawing figures, wherein like numerals denote likeelements, and wherein

FIGS. 1-6 illustrate, in cross section, a stressed MOS transistor andmethod steps for its fabrication in accordance with various embodimentsof the invention; and

FIGS. 7-9, together with FIGS. 1-4, illustrate, in cross section, astressed MOS transistor and method steps for its fabrication inaccordance with an alternate embodiment of the invention.

DETAILED DESCRIPTION

The following detailed description is merely exemplary in nature and isnot intended to limit the invention or the application and uses of theinvention. Furthermore, there is no intention to be bound by anyexpressed or implied theory presented in the preceding technical field,background, brief summary or the following detailed description.

Monocrystalline silicon, the most common semiconductor material used inthe semiconductor industry for the fabrication of semiconductor devicesand integrated circuits is characterized by a lattice constant, adimension of the silicon crystal. By substituting atoms other thansilicon in a crystal lattice, the size of the resulting crystal and thelattice constant can be changed. If a larger substitutional atom such asa germanium atom is added to the silicon lattice, the lattice constantincreases and the increase in lattice constant is proportional to theconcentration of the substitutional atom. Similarly, if a smallersubstitutional atom such as a carbon atom is added to the siliconlattice, the lattice constant decreases. Locally adding a largesubstitutional atom to a host silicon lattice creates a compressivestress on the host lattice and adding a small substitutional atom to ahost silicon lattice creates a tensile stress on the host lattice.

It is known that increasing the germanium content of embedded SiGeincreases the stress that can be applied to the channel of a PMOStransistor and thereby increased the mobility of majority carrier holesin the transistor. It is also known that having a low concentration ofgermanium at the surface of the embedded SiGe material avoids some ofthe problems that are incurred by a high germanium concentration at thesurface. Attempts have been made to achieve both the high germaniumconcentration in the bulk of the eSiGe and the low surface concentrationof germanium by the following process. Trenches are etched into thesource and drain areas of the transistor at the ends of the channel.Those trenches are then filled by a process of selective epitaxialgrowth of silicon germanium. Initially the concentration of germanium inthe reactant flow is high to cause the deposition of a high germaniumconcentration SiGe. Midway through the epitaxial growth cycle theconcentration of germanium in the reactant flow is reduced and thereduced concentration flow is maintained until the trench is filled. Theresult is a high germanium concentration SiGe under layer and a lowgermanium concentration SiGe layer at the surface. Although the deviceproduced by such a process avoided the problems that would beencountered by a high germanium concentration at the surface of theSiGe, the mobility gain was no greater than would be expected withuniformly low germanium concentration embedded SiGe filling the trench.

In the epitaxial growth process the growing material layer substantiallymimics the surface upon which it is growing. It is observed thatunfortunately the selective epitaxial growth of the high germaniumconcentration SiGe preferentially grows from the bottom of the trenchand hence the growth rate of the SiGe film on the sidewalls of thetrench is low resulting in only a thin layer of high germaniumconcentration SiGe on the sidewalls. That is, the epitaxial growthpreferentially nucleates on the crystalline structure found at thebottom of the trench rather than on the sidewall crystalline structure.The thickness of the SiGe film that covers the sidewall facing thetransistor channel is the most important in applying stress to thechannel, and the thickness realized by the conventional process isinsufficient to achieve the desired channel stress and desired mobilitygain. In accordance with the various embodiments of the invention an MOStransistor and methods for fabricating such a device are provided thatachieve sufficient thickness of high germanium concentration SiGe in theregion adjacent the channel to optimize the channel stress and mobilitygain.

FIGS. 1-6 illustrate, in cross section, a stressed MOS device 30 andmethod steps for fabricating such an MOS device in accordance withvarious embodiments of the invention. In this illustrative embodimentstressed MOS device 30 is illustrated by a single P-channel MOS (PMOS)transistor. An integrated circuit formed from stressed MOS devices suchas device 30 can include a large number of such transistors, and mayalso include unstressed PMOS transistors and stressed and unstressedN-channel MOS (NMOS) transistors as well.

Various steps in the manufacture of MOS transistors are well known andso, in the interest of brevity, many conventional steps will only bementioned briefly herein or will be omitted entirely without providingthe well known process details. Although the term “MOS device” properlyrefers to a device having a metal gate electrode and an oxide gateinsulator, that term will be used throughout to refer to anysemiconductor device that includes a conductive gate electrode (whethermetal or other conductive material) that is positioned over a gateinsulator (whether oxide or other insulator) which, in turn, ispositioned over a semiconductor substrate.

As illustrated in FIG. 1, the manufacture of a stressed MOS transistor30 in accordance with an embodiment of the invention begins withproviding a semiconductor substrate 36 in and on which such transistorsare fabricated. The initial steps in the fabrication of MOS transistor30 are conventional and will not be described in detail. Thesemiconductor substrate is preferably a silicon substrate having a (100)surface crystal orientation wherein the term “silicon substrate” and“silicon layer” are used herein to encompass the relatively puremonocrystalline silicon materials typically used in the semiconductorindustry as well as silicon admixed with other elements such asgermanium, carbon, and the like. Semiconductor substrate 36 willhereinafter be referred to for convenience but without limitation as asilicon substrate although those of skill in the semiconductor art willappreciate that other semiconductor materials could be used. Siliconsubstrate 36 may be a bulk silicon wafer (not illustrated), butpreferably is a thin monocrystalline layer of silicon 38 on aninsulating layer 40 (commonly know as silicon-on-insulator or SOI) that,in turn, is supported by a carrier wafer 42. Thin silicon layer 38typically has a thickness of less than about 200 nanometers (nm)depending on the circuit function being implemented, and in certainapplications preferably has a thickness less than about 90 nm. The thinsilicon layer preferably has a resistivity of at least about 5-40 Ohmcentimeter. The silicon can be impurity doped either N-type or P-type,but is preferably doped P-type. Dielectric insulating layer 40,typically silicon dioxide, preferably has a thickness of about 50-200nm.

Isolation regions 48 are formed that extend through monocrystallinesilicon layer 38 to dielectric insulating layer 40. The isolationregions are preferably formed by well known shallow trench isolation(STI) techniques in which trenches are etched into monocrystallinesilicon layer 38, the trenches are filled with a dielectric materialsuch as deposited silicon dioxide, and the excess silicon dioxide isremoved by chemical mechanical planarization (CMP). STI regions 48provide electrical isolation, as needed, between various devices of thecircuit that are to be formed in monocrystalline silicon layer 38.Either before or preferably after fabrication of the STI regions,selected portions of silicon layer 38 can be impurity doped, for exampleby ion implantation. For example, an N-type well 52 can be impuritydoped N-type for the fabrication of PMOS transistor 30.

A layer of gate insulator 54 is formed on surface 56 of silicon layer 38as illustrated in FIG. 2. The gate insulator may be thermally grownsilicon dioxide formed by heating the silicon substrate in an oxidizingambient, or may be a deposited insulator such as a silicon oxide,silicon nitride, a high dielectric constant insulator such asHf_(x)Si_(y)O_(z), or the like. Deposited insulators can be deposited inknown manner, for example, by chemical vapor deposition (CVD), lowpressure chemical vapor deposition (LPCVD), semi-atmospheric chemicalvapor deposition (SACVD), or plasma enhanced chemical vapor deposition(PECVD). Gate insulator 54 is here illustrated as a thermally grownsilicon dioxide layer that grows only on surface 56 of silicon layer 38.The gate insulator material is typically 1-10 nm in thickness andpreferably to a thickness of about 1-2 nm. In accordance with oneembodiment of the invention a layer of gate electrode forming material58, preferably polycrystalline silicon, is deposited onto the layer ofgate insulator. Other electrically conductive gate electrode formingmaterials such as metals and metal silicides may also be depositedproviding the material by itself or with appropriate impurity doping canset the necessary threshold voltage of the transistor. The gateelectrode forming material will hereinafter be referred to aspolycrystalline silicon although those of skill in the art willrecognize that other materials can also be employed. If the gateelectrode material is polycrystalline silicon, that material istypically deposited to a thickness of about 50-200 nm and preferably toa thickness of about 100 nm by LPCVD by the hydrogen reduction ofsilane. The layer of polycrystalline silicon is preferably deposited asundoped polycrystalline silicon and is subsequently impurity doped byion implantation. A layer of hard mask material 60 such as a layer ofsilicon nitride is deposited over the polycrystalline silicon gateelectrode forming material. The layer of masking material, if siliconnitride, can be deposited, for example, by PECVD to a thickness of about30-50 nm from the reaction of dichlorosilane and ammonia. Those of skillin the art will understand that other dielectric materials other thansilicon nitride can be deposited as the hard mask material.

As illustrated in FIG. 3, gate electrode forming material 58 and hardmask material are photolithographically patterned and etched to form agate electrode 62 overlaid by the hard mask material. Thepolycrystalline silicon can be etched in the desired pattern by, forexample, plasma etching in a Cl or HBr/O₂ chemistry and the hard maskcan be etched, for example, by plasma etching in a CHF₃, CF₄, or SF₆chemistry. Following the patterning of the gate electrode, in accordancewith one embodiment of the invention, a thin layer 64 of silicon oxideis thermally grown on the opposing sidewalls 65 and 66 of gate electrode62. The thin oxide can have a thickness, for example, of about 2-3 nm.The formation of gate electrode 62 defines a channel region 68 as thatportion at the surface of thin silicon layer 38 underlying the gateelectrode. Preferably the channel is oriented along a [110] crystaldirection so that current flow in the transistor will be in the [110]crystal direction. Thin oxide layer 64 provides a liner to separate thepolycrystalline silicon gate electrode from subsequently depositedspacer forming materials.

The method in accordance with one embodiment of the invention continuesby blanket depositing a layer of silicon nitride or other spacer formingmaterial (not illustrated) and anisotropically etching the layer to formspacers 70 overlying thin layer 64 of silicon oxide on opposingsidewalls 65 and 66 as illustrated in FIG. 4. The silicon nitride layeris deposited to a thickness of about 80-250 nm, preferably by LPCVDusing dichlorosilane and ammonia as reactants. The sidewall spacers canbe anisotropically etched, for example by reactive ion etching (RIE),using a CF₄ or CHF₃ chemistry. Recesses 72 and 74 are etched into thinsilicon layer 38 using spacers 70, gate electrode 62, and STI 48 as etchmasks. Because the sidewall spacers are used as an etch mask, therecesses are self aligned to sidewalls 65 and 66 of gate electrode 62and to channel 68 and are spaced apart from the gate electrode by adistance substantially equal to the thickness of the sidewall spacers asindicated by arrows 69. Recesses 72 and 74 are anisotropically etched,for example, by reactive ion etching (RIE) using a HBr/O₂ chemistry to adepth of about 400-600 nm as indicated by arrows 75. At least a thinportion of silicon layer 38 is left beneath bottom surface 76 of thetrenches.

Trenches 72 and 74 have side surfaces 78 and 80, respectively that facechannel 68. Bottom surface 76 is substantially parallel to and has thesame crystal orientation as surface 56 of thin silicon layer 38. Bottomsurface 76 thus lies along a (100) crystal plane. With channel 68oriented in a [110] crystal direction and side surfaces 78 and 80substantially perpendicular to surface 56, the side surfaces lie along a(011) crystal plane. In accordance with an embodiment of the inventiontrenches 72 and 74 are filled with embedded SiGe 82 by a selectiveepitaxial growth process that provides a higher growth rate on a (011)crystal plane than the growth rate on a (100) crystal plane. Theselective epitaxial growth nucleates on the side surfaces as well as onthe bottom surface, but a higher growth rate on the (011) plane can beachieved in known manner by adjusting the growth conditions such asreactant flow, growth temperature, growth pressure, and the like duringthe epitaxial growth as discussed, for example, in “SELECTIVE SILICONEPITAXY AND ORIENTATION DEPENDENCE OF GROWTH” by Rai-Choudhury, P.Schroder, D. K. Journal of the Electrochemical Society, v 120, n 5, May,1973, p 664-668. Epitaxial growth of embedded SiGe 82 is continued topartially fill trenches 72 and 74 as illustrated in FIG. 5. EmbeddedSiGe 82 is grown with a high concentration of germanium, preferablybetween about 25-40 atomic percent germanium. Embedded SiGe 82, grown inthis manner, grows a thicker layer 84 of the high germaniumconcentration SiGe on side surfaces 78 and 80 than layer 86 that growson bottom surface 76. Preferably the high germanium content SiGe on sidesurfaces 78 and 80 has a thickness of at least 10-30 nm.

The selective epitaxial growth conditions are changed to reduce thegermanium content, and the remaining portion of trenches 72 and 74 arefilled with a low concentration embedded SiGe 88 as illustrated in FIG.6. Preferably embedded SiGe 88 has a germanium concentration of about0-20 atomic percent germanium. Trenches 72 and 74 are thus filled withembedded SiGe having a thick wall of high germanium concentration alongthe side surfaces facing channel 68 and a surface of low germaniumconcentration.

In accordance with a further embodiment of the invention the structuresillustrated in FIGS. 5 and 6 are achieved by epitaxially growing highgermanium concentration embedded SiGe in a plasma environment with avertical (i.e., substantially perpendicular to surface 56) potentialbias. The epitaxial growth rate in the vertical direction, that is thegrowth rate on bottom surface 76, will be reduced by the plasma etchcomponent. After a desired thickness of high germanium concentrationSiGe is grown on the side surfaces, the epitaxial growth conditions canbe altered to reduce the germanium concentration in the low germaniumconcentration portion of the trench refill. Growth of the low germaniumcontent portion can be accomplished either with or without the plasmaenvironment.

In accordance with a further embodiment of the invention the desired endresult of a surface of low concentration germanium SiGe and asufficiently thick wall of high germanium concentration SiGe along aside surface of a trench facing the transistor channel to exert agreater stress on the channel than would be exerted by the low germaniumconcentration SiGe alone is achieved as illustrated in FIGS. 7-9 takentogether with FIGS. 1-4. The method in accordance with this embodimentof the invention begins with the same steps illustrated in FIGS. 1-4. Asillustrated in FIG. 7, trenches 72 and 74 are refilled by selectiveepitaxial growth by a layer 90 of high germanium concentration SiGe,preferably about 25-40 atomic percent germanium.

The method continues by blanket depositing a layer of silicon nitride orother spacer forming material (not illustrated) overlying the gateelectrode 62, sidewall spacers 70, and embedded SiGe 90. The layer ofspacer material can be deposited to a thickness of at least 10-30 nm by,for example, LPCVD. The layer of spacer material is anisotropicallyetched, for example by RIE, to form sidewall spacers 92 overlyingsidewall spacers 70. In an alternate embodiment (not illustrated)sidewall spacers 70 can be removed before depositing the layer of spacermaterial, the spacer material can be deposited to a thickness of about30-40 nm, and a single sidewall spacer having a thickness of 30-40 nmcan be formed. Whether two sidewall spacers or one thicker sidewallspacer are used, the sidewall spacer(s), gate electrode, and STI areused as an etch mask and trenches 94 and 96 are etched into embeddedSiGe 90 as illustrated in FIG. 8. Trenches 94 and 96 can be etched byreactive ion etching to a depth of about 15-25 nm as indicated by arrow95. Trenches 94 and 96 are self aligned to channel 68 and are spacedapart from the channel by the width of the spacer(s) as indicated byarrow 97.

As illustrated in FIG. 9, trenches 94 and 96 are refilled withselectively grown low germanium concentration epitaxial SiGe 100preferably having a germanium concentration of about 0-20 atomicpercent. Similar to the previous embodiment, the transistor has a lowgermanium concentration SiGe surface 98 and a thick wall of highgermanium concentration SiGe facing channel 68. The high germaniumconcentration SiGe has a sufficient thickness to exert more stress onthe channel of the transistor than would be exerted by the low germaniumconcentration SiGe alone.

Although not illustrated, the structures illustrated in FIGS. 6 and 9can be completed in conventional manner. Conventional steps include, forexample, removing sidewall spacers 70 and 92 and replacing them with asingle permanent sidewall spacer. The permanent sidewall spacers areused as an ion implantation mask and conductivity determining ions areimplanted into the silicon or SiGe on either side of the gate electrodeto form source and drain regions. For a PMOS transistor the conductivityions can be boron ions. As those of skill in the art will understand,more than one set of sidewall spacers can be used and more than one ionimplantation can be carried out to create source and drain extensions,create halo implants, set threshold voltage, and the like. The sidewallspacers can also be used to form self aligned metal silicide contacts tothe source and drain regions. A layer of silicide forming metal isdeposited and heated to cause the metal to react with exposed silicon orSiGe to form a metal silicide. Metal that is not in contact with exposedsilicon such as metal that is deposited on the sidewall spacers or theSTI does not react and can be removed by etching in a solution ofH₂O₂/H₂SO₄ or HNO₃/HCl. In forming a stressed MOS transistor a stressliner layer of, for example, stressed silicon nitride may be depositedover the gate electrode and metal silicide contacts. Deposition of thestress liner is followed by deposition of a dielectric layer,planarization of the dielectric layer, and etching of contact openingsthrough the dielectric layer to the metal silicide contacts. Electricalcontact to the source and drain regions can then be made by contactplugs formed in the contact openings and by interconnect metaldeposition and patterning.

The foregoing embodiments have been of methods for fabricating stressenhanced PMOS transistors. Similar methods can be used to fabricatestress enhanced NMOS transistors, and the fabrication of eitherstructure or both structures can be integrated into methods forfabricating CMOS integrated circuits including both stressed andunstressed PMOS and NMOS transistors. Fabrication of a stress enhancedNMOS transistor is similar to the methods described above except thatthe thin silicon layer is impurity doped P-type, the source and drainregions are impurity doped with N-type conductivity determining ions,and the embedded material that is epitaxially grown in the source anddrain regions should have a substitutional atom such as carbon such thatthe grown material has a lattice constant that is smaller than thelattice constant of the host material to create a longitudinal tensionalstress on the transistor channel.

While at least one exemplary embodiment has been presented in theforegoing detailed description, it should be appreciated that a vastnumber of variations exist. It should also be appreciated that theexemplary embodiment or exemplary embodiments are only examples, and arenot intended to limit the scope, applicability, or configuration of theinvention in any way. Rather, the foregoing detailed description willprovide those skilled in the art with a convenient road map forimplementing the exemplary embodiment or exemplary embodiments. Itshould be understood that various changes can be made in the functionand arrangement of elements without departing from the scope of theinvention as set forth in the appended claims and the legal equivalentsthereof.

1. A method for fabricating a stress enhanced MOS device having achannel region at a surface of a semiconductor substrate, the methodcomprising the steps of: etching trenches into the semiconductorsubstrate adjacent the channel region, each of the trenches having aside surface facing the channel region and a bottom surface; epitaxiallygrowing a first layer of SiGe having a first concentration of germaniumin the trenches to partially fill the trenches, the first layer of SiGehaving a first growth rate on the side surface and a second growth rateless than the first growth rate on the bottom surface; and epitaxiallygrowing a second layer of SiGe having a second concentration ofgermanium less than the first concentration to fill the trenches.
 2. Themethod of claim 1 wherein the semiconductor substrate is a substratecomprising silicon having a (100) crystal surface orientation, thechannel region is oriented along a [110] crystal direction, the sidesurface has a (011) crystal surface orientation, and wherein the step ofepitaxially growing a first layer comprises the step of adjustingepitaxial growth conditions to enhance epitaxial growth rate on a (011)crystal surface compared to epitaxial growth rate on a (100) crystalsurface.
 3. The method of claim 1 wherein the step of epitaxiallygrowing a first layer comprises the step of epitaxially growing a firstlayer in a plasma environment having a potential bias substantiallyperpendicular to the semiconductor substrate.
 4. The method of claim 1wherein the step of epitaxially growing a first layer comprises the stepof epitaxially growing a layer of SiGe comprising 25-40 atomic percentgermanium.
 5. The method of claim 4 wherein the step of epitaxiallygrowing a second layer comprises the step of epitaxially growing a layerof SiGe comprising 0-20 atomic percent germanium.
 6. The method of claim1 further comprising the steps of: forming a gate insulator overlyingthe channel region; forming a gate electrode overlying the gateinsulator; forming sidewall spacers on the gate electrode; and whereinthe step of etching trenches comprises the step of etching trenches inalignment with the sidewall spacers.
 7. A method for fabricating astress enhanced MOS transistor comprising the steps of: forming a gateinsulator overlying a semiconductor substrate; forming a gate electrodeoverlying the gate insulator, the gate electrode having a first edge anda second edge; etching a first trench and a second trench into thesemiconductor substrate, the first trench aligned with and spaced apartfrom the first edge by a first distance and the second trench alignedwith and spaced apart from the second edge by the first distance;epitaxially growing a first layer of SiGe having a first concentrationof germanium in the first trench and in the second trench; the firstlayer having a thickness sufficient to fill the first trench and thesecond trench; etching a third trench and a fourth trench into the firstlayer, the third trench aligned with and spaced apart from the firstside by a second distance greater than the first distance and the fourthtrench aligned with and spaced apart from the second side by the seconddistance; and epitaxially growing a second layer of SiGe having a secondconcentration of germanium less than the first concentration in thethird trench and in the fourth trench and having a second thicknesssufficient to fill the third trench and the fourth trench.
 8. The methodof claim 7 further comprising the step of: forming first sidewallspacers on the first edge and on the second edge, the first sidewallspacers having a first thickness; and wherein the step of etching afirst trench and a second trench comprises the step of etching a firsttrench and a second trench using the first sidewall spacers as an etchmask.
 9. The method of claim 8 further comprising the step of: formingsecond sidewall spacers overlying the first sidewall spacers; andwherein the step of etching a third trench and a fourth trench comprisesthe step of etching the third trench and the fourth trench using thesecond sidewall spacers as an etch mask.
 10. The method of claim 8further comprising the steps of: removing the first sidewall spacersafter the step of etching the first trench and the second trench;forming second sidewall spacers on the first edge and on the secondedge, the second sidewall spacers having a second thickness greater thanthe first thickness; and wherein the step of etching a third trench anda fourth trench comprises the step of etching the third trench and thefourth trench using the second sidewall spacers as an etch mask.
 11. Themethod of claim 7 wherein the step of epitaxially growing a first layercomprises the step of epitaxially growing a layer of SiGe comprising25-40 atomic percent germanium and wherein the step of epitaxiallygrowing a second layer comprises the step of epitaxially growing asecond layer of SiGe comprising less than 20 atomic percent germanium.12. A method for fabricating a stress enhanced MOS transistor in and ona monocrystalline semiconductor substrate having a first latticeconstant, the method comprising the steps of: forming a gate electrodeoverlying and defining a channel region in the monocrystallinesemiconductor substrate; etching a trench into the monocrystallinesemiconductor substrate adjacent the channel region and having a sidesurface facing the channel region and a bottom surface; filling thetrench with a second monocrystalline semiconductor material having afirst concentration of a substitutional atom and a third monocrystallinesemiconductor material having a second concentration of thesubstitutional atom, the second monocrystalline semiconductor materialhaving a wall thickness along the side surface sufficient to exert agreater stress on the channel region than a stress exerted by amonocrystalline semiconductor material having the second concentration.13. The method of claim 12 wherein the step of filling the trenchcomprises the step of filling the trench with a monocrystalline materialhaving a second lattice constant different that the first latticeconstant.
 14. The method of claim 12 wherein the monocrystallinesemiconductor substrate comprises a monocrystalline silicon substrateand wherein the step of filling the trench comprises the step of fillingthe trench with monocrystalline SiGe having a first concentration ofgermanium and with SiGe having a second concentration of germanium lessthan the first concentration.
 15. The method of claim 12 wherein thestep of filling the trench comprises the steps of filling the trenchwith a second monocrystalline semiconductor material comprising SiGehaving a germanium content of 25-40 atomic percent and with a thirdmonocrystalline semiconductor material comprising SiGe having agermanium content of less than 20 atomic percent.
 16. The method ofclaim 12 wherein the step of filling the trench comprises filling thetrench with a second monocrystalline semiconductor material comprisingSiGe having a wall thickness along the side surface of at least 10 nm.17. The method of claim 12 wherein the step of filling the trenchcomprises the steps of: epitaxially growing first SiGe having a firstconcentration of germanium to fill the trench; etching a second trenchinto the first SiGe, the second trench spaced apart from the channelregion by the wall thickness; and epitaxially growing second SiGe havinga second concentration of germanium less than the first concentration tofill the second trench.
 18. The method of claim 17 wherein the step offilling the trench comprises the step of epitaxially growing SiGe havinga germanium concentration of 25-40 atomic percent and the step offilling the second trench comprises the step of epitaxially growing SiGehaving a germanium concentration of less than 20 atomic percent.
 19. Themethod of claim 12 wherein the step of filling the trench comprises thesteps of: initiating growth of the second monocrystalline semiconductormaterial with an epitaxial growth process having an accelerated growthrate along the side surface in comparison to the bottom surface;reducing concentration of the substitutional atom; and epitaxiallygrowing the third monocrystalline semiconductor material to completefilling of the trench.
 20. A stress enhanced MOS transistor comprising:a semiconductor substrate having a surface; a channel region at thesurface of the semiconductor substrate; a first region of SiGe having afirst germanium concentration embedded in the semiconductor substrateand having a bottom portion and a side portion adjacent the channelregion; a second region of SiGe having a second germanium concentrationless than the first germanium concentration embedded in the first regionwherein the side portion has a greater thickness than the bottomportion.